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FSL(Now is NXP) used DIMM slot on T1040RDB and T2080QDS board. And my company first customized board used DIMM also.
But, due to the reliability, we decided change DIMM slot to on board DDR chip, so I need make it work.
The fsl support one powerful tool named ‘Code warrior’ and it has a plugin named ‘QCVS’. We can validate DDR configurates by it. See Ref.4 for more information.
After validate, we should make some change to U-Boot.
First add ‘CONFIG_SYS_DDR_RAW_TIMING’ defined in board config.h file.
Then add followed code into board/ddr.c
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#ifdef CONFIG_SYS_DDR_RAW_TIMING /* 2GB discrete DDR3 on board */ dimm_params_t ddr_raw_timing = { .rank_density = 0x40000000, /**< 1GB */ .capacity = 0x800000000, /**< 2GB */ .burst_lengths_bitmask = 0x0c, .n_ranks = 2, .data_width = 64, /**< 64bit */ .primary_sdram_width = 64, /**< 64bit */ .ec_sdram_width = 0, /**< ECC width */ .registered_dimm = 0, .mirrored_dimm = 1, .device_width = 8, .n_row_addr = 14, .n_col_addr = 10, .edc_config = 0, /**< 0 = none, 1 = parity, 2 = ECC */ .n_banks_per_sdram_device = 8, /* SDRAM clock periods */ .tckmin_x_ps = 1250, /* SPD-defined CAS latencies */ .caslat_x = 3824, .taa_ps = 13125, .trcd_ps = 13125, .trp_ps = 13125, .tras_ps = 36000, .tfaw_ps = 30000, .twr_ps = 15000, .twtr_ps = 7500, .trfc_ps = 110000, .trrd_ps = 6000, .trtp_ps = 7500, .trc_ps = 49125, .refresh_rate_ps = 3900000, }; int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, unsigned int controller_number, unsigned int dimm_number) { const char dimm_model[] = "Fixed DDR3L on board"; if (((controller_number == 0) && (dimm_number == 0)) || ((controller_number == 1) && (dimm_number == 0))) { memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); } return 0; } #endif |
dimm_params_t description:
| Member | Description |
|---|---|
| rank_density | 每一个Rank的DDR容量，即一个CS对应的容量，单位字节 |
| capacity | 总容量，单位字节 |
| burst_lengths_bitmask | |
| n_ranks | Rank的数量，即使用了几根CS信号 |
| data_width | 数据宽度，DATA和ECC数据宽度的总和，一般为64/72(with ECC) |
| primary_sdram_width | DATA数据宽度，一般为64 |
| ec_sdram_width | ECC的数据宽度，一般为0/8(with ECC) |
| registered_dimm | 一般为0 |
| mirrored_dimm | 是否支持address mirror，see Ref.2 for more information |
| device_width | DDR颗粒数据宽度，根据实际芯片的数据宽度来定，一般为8/16 |
| n_row_addr | DDR颗粒的Row Address |
| n_col_addr | DDR颗粒的Column Address |
| edc_config | 0 = none 1 = parity 2 = ECC |
| n_banks_per_sdram_device | DDR颗粒的Bank address |
| tckmin_x_ps | |
| caslat_x | |
| taa_ps | |
| trcd_ps | |
| trp_ps | |
| tras_ps | |
| tfaw_ps | |
| twr_ps | |
| twtr_ps | |
| trfc_ps | |
| trrd_ps | |
| trtp_ps | |
| trc_ps | |
| refresh_rate_ps |
Third fill struct with QCVS validate parameters into board/ddr.h, seems as:
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/* * These tables contain all valid speeds we want to override with board * specific parameters. datarate_mhz_high values need to be in ascending order * for each n_ranks group. */ static const struct board_specific_parameters udimm0[] = { /* * memory controller 0 * num| hi| rank| clk| wrlvl | wrlvl * ranks| mhz| GB |adjst| start | ctl2 */ #ifdef CONFIG_SYS_FSL_DDR4 {2, 1600, 4, 4, 6, 0x07090A0c, 0x0e0f100a}, #elif defined(CONFIG_SYS_FSL_DDR3) {2, 833, 4, 4, 6, 0x06060607, 0x08080807}, {2, 833, 0, 4, 6, 0x06060607, 0x08080807}, {2, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09}, {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09}, {2, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A}, {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A}, {1, 833, 4, 4, 6, 0x06060607, 0x08080807}, {1, 833, 0, 4, 6, 0x06060607, 0x08080807}, {1, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09}, {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09}, {1, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A}, {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A}, #else #error DDR type not defined #endif {} }; |
Reference
- T2081 DDR3L on-board initialisation
- DDR3 memory mirroring – PCB layout
- U-Boot:board/freescale/t102xrdb/ddr.c
- QCVS_DDR_User_Guide.pdf
- Micron:4Gb_DDR3L.pdf
