{"id":1622,"date":"2016-09-02T17:32:37","date_gmt":"2016-09-02T09:32:37","guid":{"rendered":"http:\/\/kaoru.tech\/?p=1622"},"modified":"2016-09-02T17:46:20","modified_gmt":"2016-09-02T09:46:20","slug":"port-on-board-ddr-chip-on-qoriq-t12-series","status":"publish","type":"post","link":"http:\/\/kaoru.tech:7000\/wordpress\/?p=1622","title":{"rendered":"Port on Board DDR Chip on QorIQ T1&2 Series"},"content":{"rendered":"

FSL(Now is NXP) used DIMM slot on T1040RDB and T2080QDS board. And my company first customized\u00a0board used DIMM also.<\/p>\n

But, due to the reliability, we decided change DIMM slot to on board DDR chip, so I need make it work.<\/p>\n

The fsl support one powerful tool named ‘Code warrior’ and it has a plugin named ‘QCVS’. We can validate DDR configurates by it. See Ref.4 for more information.<\/p>\n

After validate, we should make some change to U-Boot.<\/p>\n

First add ‘CONFIG_SYS_DDR_RAW_TIMING’ defined in board config.h file.<\/p>\n

<\/p>\n

Then add followed code into\u00a0board\/ddr.c<\/p>\n

#ifdef CONFIG_SYS_DDR_RAW_TIMING\r\n\/* 2GB discrete DDR3 on board *\/\r\ndimm_params_t ddr_raw_timing = {\r\n        .rank_density = 0x40000000,     \/**< 1GB        *\/\r\n        .capacity = 0x800000000,        \/**< 2GB        *\/\r\n        .burst_lengths_bitmask = 0x0c,\r\n        .n_ranks = 2,\r\n        .data_width = 64,               \/**< 64bit      *\/\r\n        .primary_sdram_width = 64,      \/**< 64bit      *\/\r\n        .ec_sdram_width = 0,            \/**< ECC width  *\/\r\n        .registered_dimm = 0,\r\n        .mirrored_dimm = 1,\r\n        .device_width = 8,\r\n        .n_row_addr = 14,\r\n        .n_col_addr = 10,\r\n        .edc_config = 0,                \/**< 0 = none, 1 = parity, 2 = ECC *\/\r\n        .n_banks_per_sdram_device = 8,\r\n\r\n        \/* SDRAM clock periods *\/\r\n        .tckmin_x_ps = 1250,\r\n\r\n        \/* SPD-defined CAS latencies *\/\r\n        .caslat_x = 3824,\r\n        .taa_ps = 13125,\r\n        .trcd_ps = 13125,\r\n        .trp_ps = 13125,\r\n        .tras_ps = 36000,\r\n        .tfaw_ps = 30000,\r\n        .twr_ps = 15000,\r\n        .twtr_ps = 7500,\r\n        .trfc_ps = 110000,\r\n        .trrd_ps = 6000,\r\n        .trtp_ps = 7500,\r\n        .trc_ps = 49125,\r\n        .refresh_rate_ps = 3900000,\r\n};\r\n\r\nint fsl_ddr_get_dimm_params(dimm_params_t *pdimm,\r\n                unsigned int controller_number,\r\n                unsigned int dimm_number)\r\n{\r\n        const char dimm_model[] = \"Fixed DDR3L on board\";\r\n\r\n        if (((controller_number == 0) && (dimm_number == 0)) ||\r\n            ((controller_number == 1) && (dimm_number == 0))) {\r\n                memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));\r\n                memset(pdimm->mpart, 0, sizeof(pdimm->mpart));\r\n                memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);\r\n        }\r\n\r\n        return 0;\r\n}\r\n#endif<\/pre>\n
dimm_params_t description:<\/p>\n
\n\r\n\r\n
Member<\/th>\nDescription<\/th>\n<\/tr>\n<\/thead>\n
rank_density<\/td>\n\u6bcf\u4e00\u4e2aRank\u7684DDR\u5bb9\u91cf\uff0c\u5373\u4e00\u4e2aCS\u5bf9\u5e94\u7684\u5bb9\u91cf\uff0c\u5355\u4f4d\u5b57\u8282<\/td>\n<\/tr>\n\r\n
capacity<\/td>\n\u603b\u5bb9\u91cf\uff0c\u5355\u4f4d\u5b57\u8282<\/td>\n<\/tr>\n\r\n
burst_lengths_bitmask<\/td>\n<\/td>\n<\/tr>\n\r\n
n_ranks<\/td>\nRank\u7684\u6570\u91cf\uff0c\u5373\u4f7f\u7528\u4e86\u51e0\u6839CS\u4fe1\u53f7<\/td>\n<\/tr>\n\r\n
data_width<\/td>\n\u6570\u636e\u5bbd\u5ea6\uff0cDATA\u548cECC\u6570\u636e\u5bbd\u5ea6\u7684\u603b\u548c\uff0c\u4e00\u822c\u4e3a64\/72(with ECC)<\/td>\n<\/tr>\n\r\n
primary_sdram_width<\/td>\nDATA\u6570\u636e\u5bbd\u5ea6\uff0c\u4e00\u822c\u4e3a64<\/td>\n<\/tr>\n\r\n
ec_sdram_width<\/td>\nECC\u7684\u6570\u636e\u5bbd\u5ea6\uff0c\u4e00\u822c\u4e3a0\/8(with ECC)<\/td>\n<\/tr>\n\r\n
registered_dimm<\/td>\n\u4e00\u822c\u4e3a0<\/td>\n<\/tr>\n\r\n
mirrored_dimm<\/td>\n\u662f\u5426\u652f\u6301address mirror\uff0csee Ref.2 for more information<\/td>\n<\/tr>\n\r\n
device_width<\/td>\nDDR\u9897\u7c92\u6570\u636e\u5bbd\u5ea6\uff0c\u6839\u636e\u5b9e\u9645\u82af\u7247\u7684\u6570\u636e\u5bbd\u5ea6\u6765\u5b9a\uff0c\u4e00\u822c\u4e3a8\/16<\/td>\n<\/tr>\n\r\n
n_row_addr<\/td>\nDDR\u9897\u7c92\u7684Row Address<\/td>\n<\/tr>\n\r\n
n_col_addr<\/td>\nDDR\u9897\u7c92\u7684Column Address<\/td>\n<\/tr>\n\r\n
edc_config<\/td>\n0 = none
1 = parity
2 = ECC<\/td>\n<\/tr>\n\r\n
n_banks_per_sdram_device<\/td>\nDDR\u9897\u7c92\u7684Bank address<\/td>\n<\/tr>\n\r\n
tckmin_x_ps<\/td>\n<\/td>\n<\/tr>\n\r\n
caslat_x<\/td>\n<\/td>\n<\/tr>\n\r\n
taa_ps<\/td>\n<\/td>\n<\/tr>\n\r\n
trcd_ps<\/td>\n<\/td>\n<\/tr>\n\r\n
trp_ps<\/td>\n<\/td>\n<\/tr>\n\r\n
tras_ps<\/td>\n<\/td>\n<\/tr>\n\r\n
tfaw_ps<\/td>\n<\/td>\n<\/tr>\n\r\n
twr_ps<\/td>\n<\/td>\n<\/tr>\n\r\n
twtr_ps<\/td>\n<\/td>\n<\/tr>\n\r\n
trfc_ps<\/td>\n<\/td>\n<\/tr>\n\r\n
trrd_ps<\/td>\n<\/td>\n<\/tr>\n\r\n
trtp_ps<\/td>\n<\/td>\n<\/tr>\n\r\n
trc_ps<\/td>\n<\/td>\n<\/tr>\n\r\n
refresh_rate_ps<\/td>\n<\/td>\n<\/tr>\n<\/tbody><\/table><\/div>\n
<\/p>\n
Third fill struct with QCVS validate parameters into board\/ddr.h, seems as:<\/p>\n
\/*\r\n * These tables contain all valid speeds we want to override with board\r\n * specific parameters. datarate_mhz_high values need to be in ascending order\r\n * for each n_ranks group.\r\n *\/\r\n\r\nstatic const struct board_specific_parameters udimm0[] = {\r\n        \/*\r\n         * memory controller 0\r\n         *   num|  hi| rank|  clk| wrlvl |   wrlvl\r\n         * ranks| mhz| GB  |adjst| start |   ctl2\r\n         *\/\r\n#ifdef CONFIG_SYS_FSL_DDR4\r\n        {2,  1600, 4, 4,     6, 0x07090A0c, 0x0e0f100a},\r\n#elif defined(CONFIG_SYS_FSL_DDR3)\r\n        {2,  833,  4, 4,     6, 0x06060607, 0x08080807},\r\n        {2,  833,  0, 4,     6, 0x06060607, 0x08080807},\r\n        {2,  1350, 4, 4,     7, 0x0708080A, 0x0A0B0C09},\r\n        {2,  1350, 0, 4,     7, 0x0708080A, 0x0A0B0C09},\r\n        {2,  1666, 4, 4,     7, 0x0808090B, 0x0C0D0E0A},\r\n        {2,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A},\r\n        {1,  833,  4, 4,     6, 0x06060607, 0x08080807},\r\n        {1,  833,  0, 4,     6, 0x06060607, 0x08080807},\r\n        {1,  1350, 4, 4,     7, 0x0708080A, 0x0A0B0C09},\r\n        {1,  1350, 0, 4,     7, 0x0708080A, 0x0A0B0C09},\r\n        {1,  1666, 4, 4,     7, 0x0808090B, 0x0C0D0E0A},\r\n        {1,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A},\r\n#else\r\n#error DDR type not defined\r\n#endif\r\n        {}\r\n};<\/pre>\n
 <\/p>\n
Reference<\/h2>\n
    \n
  1. T2081 DDR3L on-board initialisation<\/a><\/li>\n
  2. DDR3 memory mirroring \u2013 PCB layout<\/a><\/li>\n
  3. U-Boot:board\/freescale\/t102xrdb\/ddr.c<\/li>\n
  4. QCVS_DDR_User_Guide.pdf<\/a><\/li>\n
  5. Micron:4Gb_DDR3L.pdf<\/li>\n<\/ol>\n","protected":false},"excerpt":{"rendered":"
    FSL(Now is NXP) used DIMM slot on T1040RDB and T2080QDS board. And my company first customized\u00a0board used DIMM also. But, due to the reliability, we decided change DIMM slot to…<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"ngg_post_thumbnail":0,"footnotes":""},"categories":[19],"tags":[148,209,199],"class_list":["post-1622","post","type-post","status-publish","format-standard","hentry","category-powerpc","tag-ddr","tag-powerpc","tag-qoriq"],"_links":{"self":[{"href":"http:\/\/kaoru.tech:7000\/wordpress\/index.php?rest_route=\/wp\/v2\/posts\/1622","targetHints":{"allow":["GET"]}}],"collection":[{"href":"http:\/\/kaoru.tech:7000\/wordpress\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"http:\/\/kaoru.tech:7000\/wordpress\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"http:\/\/kaoru.tech:7000\/wordpress\/index.php?rest_route=\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"http:\/\/kaoru.tech:7000\/wordpress\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=1622"}],"version-history":[{"count":14,"href":"http:\/\/kaoru.tech:7000\/wordpress\/index.php?rest_route=\/wp\/v2\/posts\/1622\/revisions"}],"predecessor-version":[{"id":1636,"href":"http:\/\/kaoru.tech:7000\/wordpress\/index.php?rest_route=\/wp\/v2\/posts\/1622\/revisions\/1636"}],"wp:attachment":[{"href":"http:\/\/kaoru.tech:7000\/wordpress\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=1622"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"http:\/\/kaoru.tech:7000\/wordpress\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=1622"},{"taxonomy":"post_tag","embeddable":true,"href":"http:\/\/kaoru.tech:7000\/wordpress\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=1622"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}