\u8fd9\u4e24\u5929\u8c03\u8bd5\u4e86\u81ea\u5df1\u516c\u53f8\u505a\u7684fsl T2081\u677f\u5b50\uff0c\u9047\u5230\u4e86\u4e00\u4e9b\u5751\uff0c\u4e0d\u8fc7\u6700\u540e\u8fd8\u662f\u641e\u5b9a\u4e86\uff0c\u8bb0\u5f55\u4e4b\u5df2\u5907\u5019\u67e5\u3002<\/p>\n
\u4e3b\u8981\u662f\u65f6\u949f\u95ee\u9898\uff0c\u7531\u4e8e\u6211\u4eec\u7684\u5728\u4e00\u5757\u4e3b\u677f\u4e0a\u517c\u5bb9\u4e861022\u30011042\u548c2081\u4e09\u79cd\u5e73\u53f0\u3002\u6240\u4ee5SYS\/DDR reference clock\u4e5f\u662f\u4e00\u6837\u7684\uff0c\u90fd\u662f100M\u7684SYS clock\u548c66.66M\u7684DDR clock\u3002<\/p>\n
\u4e4b\u524d\u8c03\u8bd51042\u7684\u65f6\u5019\u6ca1\u6709\u95ee\u9898\uff0c\u4f46\u662f\u5728\u8c03\u8bd52081\u7684\u65f6\u5019\uff0cSD\u5361\u542f\u52a8\u6253\u5370\u4e86\u4e00\u5806\u4e71\u7801\uff0c\u7ecf\u8fc7\u6bd4\u8f83\u611f\u89c9\u4e71\u53d1\u5c31\u662fCPU\u9001\u51fa\u6765\u7684\u542f\u52a8\u4fe1\u606f\uff0c\u4e8e\u662f\u7528\u793a\u6ce2\u5668\u91cf\u4e4b\uff0c\u53d1\u73b0\u6bcf\u4e2abit\u4e3a5.6us\uff0c\u548c115200\u60f3\u6bd4\uff0c\u5dee\u4e0d\u591a\u4e3a\u5bf9\u65b9\u76842\/3\u3002\u4e8e\u662f\u76f4\u63a5\u4fee\u6539”board\/freescale\/t208xqds\/spl.c”\u6587\u4ef6\u4e2dboard_init_f\u51fd\u6570\u768416550\u7684\u521d\u59cb\u5316\uff0c\u5982\u4e0b\uff1a<\/p>\n
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,\r\n- ccb_clk \/ 16 \/ CONFIG_BAUDRATE);\r\n+ ccb_clk \/ 16 \/ CONFIG_BAUDRATE * 3 \/ 2);\r\n \r\n #if defined(CONFIG_SPL_MMC_BOOT)<\/pre>\n\u91cd\u65b0\u70e7\u5199\u4fbf\u53ef\u4ee5\u663e\u793a\u6b63\u5e38\u4fe1\u606f\u3002<\/p>\n
\u4f46\u662f\uff0c\u662f\u4ec0\u4e48\u539f\u56e0\u5bfc\u81f4\u57fa\u51c6\u65f6\u949f\u7684\u95ee\u9898\u5462\uff1f\u56e0\u4e3a\u65f6\u949f\u5dee2\/3\uff0c\u6240\u4ee5\u6211\u5f00\u59cb\u6000\u7591\u662f\u5426\u662f\u4e3b\u677f\u4e0aDDR\u548cSYS\u7684\u65f6\u949f\u82af\u7247\u710a\u53cd\u4e86\uff0c\u4e0d\u8fc7\u53d1\u73b0\u5e76\u6ca1\u6709\u710a\u53cd\u3002<\/p>\n
\u540e\u6765\u60f3\u5230\uff0c\u8bc4\u4f30\u677f\u662f66.66\/133.33\u7684\u65f6\u949f\uff0c\u800c\u4e14CPU\u80af\u5b9a\u5141\u8bb8\u4e00\u5b9a\u8303\u56f4\u7684\u65f6\u949f\u8f93\u5165\uff0c\u6240\u4ee5\u8fd9\u4e2a\u53c2\u8003\u65f6\u949fCPU\u80af\u5b9a\u4e0d\u77e5\u9053\uff0c\u9700\u8981\u4eba\u5de5\u8bbe\u7f6e\uff0c\u4e8e\u662f\u67e5\u67e5BSP\u4ee3\u7801\uff0c<\/p>\n
\u5728”board\/freescale\/t208xqds\/spl.c”\u4e2d\uff1a<\/p>\n
unsigned long get_board_sys_clk(void)\r\n{ \r\n u8 sysclk_conf = QIXIS_READ(brdcfg[1]);\r\n\r\n switch (sysclk_conf & 0x0F) {\r\n case QIXIS_SYSCLK_83:\r\n return 83333333;\r\n case QIXIS_SYSCLK_100:\r\n return 100000000;\r\n case QIXIS_SYSCLK_125:\r\n return 125000000;\r\n case QIXIS_SYSCLK_133:\r\n return 133333333;\r\n case QIXIS_SYSCLK_150:\r\n return 150000000;\r\n case QIXIS_SYSCLK_160:\r\n return 160000000;\r\n case QIXIS_SYSCLK_166:\r\n return 166666666;\r\n }\r\n return 66666666;\r\n}\r\n\r\nunsigned long get_board_ddr_clk(void)\r\n{\r\n u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);\r\n\r\n switch ((ddrclk_conf & 0x30) >> 4) {\r\n case QIXIS_DDRCLK_100:\r\n return 100000000;\r\n case QIXIS_DDRCLK_125:\r\n return 125000000;\r\n case QIXIS_DDRCLK_133:\r\n return 133333333;\r\n }\r\n return 66666666;\r\n}<\/pre>\n\u540c\u6837\u5728”board\/freescale\/t208xqds\/t208xqds.c”\u4e2d\u4e5f\u6709\uff0c\u53ea\u662fspl.c\u662f\u7ed9FPL\u7528\u7684\uff0ct208xqds.c\u662f\u7ed9NOR\u542f\u52a8\u6216\u8005SPL\u4f7f\u7528\u7684\u3002<\/p>\n
\u67e5\u4e86\u4e00\u4e0bQIXIS_READ\u662f\u8bfbCPLD\u5bc4\u5b58\u5668\u4fe1\u606f\uff0c\u539f\u6765FSL\u901a\u8fc7\u8fd9\u79cd\u65b9\u6cd5\u5c31\u53ef\u4ee5\u5728\u4e0d\u6539\u4ee3\u7801\u7684\u524d\u63d0\u4e0b\u901a\u8fc7\u62e8\u7801\u4fee\u6539\u53c2\u8003\u65f6\u949f\u3002<\/p>\n
\u4e8e\u662f\u76f4\u63a5\u5199\u6b7bsys\/ddr\u4e3a100\/66.66\u3002\u542f\u52a8\u540e\u663e\u793a\uff1a<\/p>\n
SD boot...\r\nInitializing....using SPD\r\nDDR clock (MCLK cycle 625 ps) is faster than the slowest DIMM(s) (tCKmin 1250 ps) can support.\r\nThe choosen cas latency 37 is too large\r\nWARNING: Calling __hwconfig without a buffer and before environment is ready\r\nWARNING: Calling __hwconfig without a buffer and before environment is ready\r\nWARNING: Calling __hwconfig without a buffer and before environment is ready\r\nWARNING: Calling __hwconfig without a buffer and before environment is ready\r\nError: board specific timing not foundfor data rate 3199 MT\/s\r\nTrying to use the highest speed (2140) parameters\r\nError: WRREC doesn't support 24 clocks\r\nWarning: CWL is out of range\r\nError: unsupported write recovery for mode register wr_mclk = 24\r\nError: unsupported cas latency for mode register\r\nWarning: CWL is out of range\r\nWaiting for D_INIT timeout. Memory may not work.<\/pre>\n\u663e\u793aCPU\u7684DDR clock\u592a\u5feb\uff0c\u8fd9\u4e2a\u95ee\u9898\u4e4b\u524d\u5728T4240\u4e0a\u9047\u5230\u8fc7\uff0c\u662f\u56e0\u4e3aRCW\u914d\u7f6eDDR pll\u548cDDR Latency\u7684\u95ee\u9898\uff0c\u4f46\u662f\u67e5\u4e86RCW\u914d\u7f6e\u5b57\u4e2d\u7684MEM_PLL_RAT\u548cDRAM LAT\u90fd\u6ca1\u6709\u95ee\u9898\uff0c\u53ea\u80fd\u8ddf\u8e2a\u4ee3\u7801\u4e86\u3002<\/p>\n
\u8c03\u7528\u6d41\u7a0b\u4e3a\uff1a<\/p>\n
board\/freescale\/t208xqds\/ddr.c:\u00a0ddr_freq = get_ddr_freq(0) \/ 1000000;<\/p>\n
arch\/powerpc\/cpu\/mpc85xx\/speed.c:\u00a0gd->mem_clk = sys_info.freq_ddrbus;<\/p>\n
\u5728”get_sys_info”\u51fd\u6570\u4e2d\uff1a<\/p>\n
\/* T4240\/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of\r\n * T4240\/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0\r\n * it uses 6.\r\n * T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0\r\n *\/\r\n#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \\\r\n defined(CONFIG_PPC_T4080) || defined(CONFIG_PPC_T2080) || \\\r\n defined(CONFIG_PPC_T2081)\r\n svr = get_svr();\r\n switch (SVR_SOC_VER(svr)) {\r\n case SVR_T4240:\r\n case SVR_T4160:\r\n case SVR_T4120:\r\n case SVR_T4080:\r\n if (SVR_MAJ(svr) >= 2)\r\n mem_pll_rat *= 2;\r\n break;\r\n case SVR_T2080:\r\n case SVR_T2081:\r\n if ((SVR_MAJ(svr) > 1) || (SVR_MIN(svr) >= 1))\r\n mem_pll_rat *= 2;\r\n break;\r\n default:\r\n break;\r\n }\r\n#endif<\/pre>\n\u539f\u6765T2080 rev 1.1\u548c\u4ee5\u4e0a\u7248\u672c\u6709\u4e00\u4e2aBUG\uff0c\u5728\u6b64\u7248\u672c\u4e0a\u9700\u8981\u914d\u7f6e\u6b63\u5e38PLL\u7684\u4e00\u534a\uff0c\u641e\u5b9a\u3002<\/p>\n","protected":false},"excerpt":{"rendered":"
\u8fd9\u4e24\u5929\u8c03\u8bd5\u4e86\u81ea\u5df1\u516c\u53f8\u505a\u7684fsl T2081\u677f\u5b50\uff0c\u9047\u5230\u4e86\u4e00\u4e9b\u5751\uff0c\u4e0d\u8fc7\u6700\u540e\u8fd8\u662f\u641e\u5b9a\u4e86\uff0c\u8bb0\u5f55\u4e4b\u5df2\u5907\u5019\u67e5\u3002 \u4e3b\u8981\u662f\u65f6\u949f\u95ee\u9898\uff0c\u7531\u4e8e\u6211\u4eec\u7684\u5728\u4e00\u5757\u4e3b\u677f\u4e0a\u517c\u5bb9\u4e861022\u30011042\u548c2081\u4e09\u79cd\u5e73\u53f0\u3002\u6240\u4ee5SYS\/DDR reference clock\u4e5f\u662f\u4e00\u6837\u7684\uff0c\u90fd\u662f100M\u7684SYS clock\u548c66.66M\u7684DDR clock\u3002 \u4e4b\u524d\u8c03\u8bd51042\u7684\u65f6\u5019\u6ca1\u6709\u95ee\u9898\uff0c\u4f46\u662f\u5728\u8c03\u8bd52081\u7684\u65f6\u5019\uff0cSD\u5361\u542f\u52a8\u6253\u5370\u4e86\u4e00\u5806\u4e71\u7801\uff0c\u7ecf\u8fc7\u6bd4\u8f83\u611f\u89c9\u4e71\u53d1\u5c31\u662fCPU\u9001\u51fa\u6765\u7684\u542f\u52a8\u4fe1\u606f\uff0c\u4e8e\u662f\u7528\u793a\u6ce2\u5668\u91cf\u4e4b\uff0c\u53d1\u73b0\u6bcf\u4e2abit\u4e3a5.6us\uff0c\u548c115200\u60f3\u6bd4\uff0c\u5dee\u4e0d\u591a\u4e3a\u5bf9\u65b9\u76842\/3\u3002\u4e8e\u662f\u76f4\u63a5\u4fee\u6539”board\/freescale\/t208xqds\/spl.c”\u6587\u4ef6\u4e2dboard_init_f\u51fd\u6570\u768416550\u7684\u521d\u59cb\u5316\uff0c\u5982\u4e0b\uff1a NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, – ccb_clk \/ 16 \/ CONFIG_BAUDRATE); + ccb_clk \/ 16 \/ CONFIG_BAUDRATE * 3 \/ 2); #if defined(CONFIG_SPL_MMC_BOOT) \u91cd\u65b0\u70e7\u5199\u4fbf\u53ef\u4ee5\u663e\u793a\u6b63\u5e38\u4fe1\u606f\u3002 \u4f46\u662f\uff0c\u662f\u4ec0\u4e48\u539f\u56e0\u5bfc\u81f4\u57fa\u51c6\u65f6\u949f\u7684\u95ee\u9898\u5462\uff1f\u56e0\u4e3a\u65f6\u949f\u5dee2\/3\uff0c\u6240\u4ee5\u6211\u5f00\u59cb\u6000\u7591\u662f\u5426\u662f\u4e3b\u677f\u4e0aDDR\u548cSYS\u7684\u65f6\u949f\u82af\u7247\u710a\u53cd\u4e86\uff0c\u4e0d\u8fc7\u53d1\u73b0\u5e76\u6ca1\u6709\u710a\u53cd\u3002 \u540e\u6765\u60f3\u5230\uff0c\u8bc4\u4f30\u677f\u662f66.66\/133.33\u7684\u65f6\u949f\uff0c\u800c\u4e14CPU\u80af\u5b9a\u5141\u8bb8\u4e00\u5b9a\u8303\u56f4\u7684\u65f6\u949f\u8f93\u5165\uff0c\u6240\u4ee5\u8fd9\u4e2a\u53c2\u8003\u65f6\u949fCPU\u80af\u5b9a\u4e0d\u77e5\u9053\uff0c\u9700\u8981\u4eba\u5de5\u8bbe\u7f6e\uff0c\u4e8e\u662f\u67e5\u67e5BSP\u4ee3\u7801\uff0c…<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"ngg_post_thumbnail":0,"footnotes":""},"categories":[14],"tags":[130,287],"class_list":["post-1593","post","type-post","status-publish","format-standard","hentry","category-embedded","tag-freescale","tag-t2081"],"_links":{"self":[{"href":"http:\/\/kaoru.tech:7000\/wordpress\/index.php?rest_route=\/wp\/v2\/posts\/1593","targetHints":{"allow":["GET"]}}],"collection":[{"href":"http:\/\/kaoru.tech:7000\/wordpress\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"http:\/\/kaoru.tech:7000\/wordpress\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"http:\/\/kaoru.tech:7000\/wordpress\/index.php?rest_route=\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"http:\/\/kaoru.tech:7000\/wordpress\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=1593"}],"version-history":[{"count":1,"href":"http:\/\/kaoru.tech:7000\/wordpress\/index.php?rest_route=\/wp\/v2\/posts\/1593\/revisions"}],"predecessor-version":[{"id":1594,"href":"http:\/\/kaoru.tech:7000\/wordpress\/index.php?rest_route=\/wp\/v2\/posts\/1593\/revisions\/1594"}],"wp:attachment":[{"href":"http:\/\/kaoru.tech:7000\/wordpress\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=1593"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"http:\/\/kaoru.tech:7000\/wordpress\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=1593"},{"taxonomy":"post_tag","embeddable":true,"href":"http:\/\/kaoru.tech:7000\/wordpress\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=1593"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}